1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a circuit operating on the basis of a clock signal.
2. Description of the Prior Art
In relation to an ASIC (application specific integrated (circuit) readily implementing a device for a specific application with CAD (computer aided design), a gate array system, a standard cell system and an embedded array system are well known in general as methods of efficiently designing a semi-custom LSI.
In the gate array system, basic cells covered with transistors in the form of arrays are arranged and wired for forming a logic circuit, and the design TAT (turn-around time) is advantageously reduced.
In the standard cell system, optimally designed verified macro cell parts are previously registered in a design database for CAD so that the macro cell parts are arbitrarily combined by CAD. According to this method, large-sized macro cell parts such as a CPU (central processing unit) and a memory are easy to design although the design TAT is longer than that in the gate array system.
In the embedded array system, employing the advantages of both of the gate array system and the standard cell system, macro cell parts of standard cells are embedded in a random logic part of a gate array.
When designing an ASIC, power supply wires are necessary for fixing signal lines in the circuit to a power supply potential or a ground potential. According to Japanese Patent Laying-Open No. 8-125025 (1996), for example, power supply potential wires and ground potential wires are provided in the form of rings for enclosing a microcomputer core as macro cell parts in a design of an ASIC microcomputer.
In a synchronous design for operating a plurality of logic circuits in synchronization with a clock signal, a large current instantaneously flows to power supply wires since the clock signal makes transition an extremely large number of times as compared with other signals and the logic circuits are designed to simultaneously operate due to the synchronous design. Thus, the power supply wires readily cause voltage drops. When the power supply wires cause voltage drops, data signals processed in the logic circuits cause noise, waveform rounding or delay degradation, leading to malfunctions.
An object of the present invention is to provide a semiconductor integrated circuit capable of suppressing occurrence of a malfunction resulting from fluctuation of a power supply voltage to the minimum.
A semiconductor integrated device according to the present invention comprises a single or plurality of logic circuits each including a first circuit for inputting a clock signal and a second circuit operating in synchronization with the clock signal input by the first circuit, a first power supply wire connected with the first circuit of each logic circuit and a second power supply wire provided independently of the first power supply wire and connected with the second circuit of each logic circuit.
In the semiconductor integrated circuit, the first circuit of each logic circuit is connected with the first power supply wire, and the second circuit of each logic circuit is connected with the second power supply wire provided independently of the first power supply wire. Also when the first power supply wire causes a large voltage drop, therefore, no influence thereof is exerted on the second power supply wire. Therefore, a data signal processed in the first circuit can be prevented from noise, waveform rounding or delay degradation, for preventing a malfunction.
The semiconductor integrated circuit may further comprise a first input terminal for externally supplying a power supply voltage to the first power supply wire and a second input terminal for externally supplying the power supply voltage to the second power supply wire, and the first and second input terminals may be provided in common. In this case, the number of external pins can be reduced.
The semiconductor integrated circuit may further comprise a semiconductor substrate formed with the single or plurality of logic circuits, the first power supply wire and the second power supply wire, and the first and second input terminals may include a bonding pad formed on the semiconductor substrate in common. In this case, voltage drops in the first and second input terminals can be ignored.
The semiconductor integrated circuit may further comprise a first input terminal for externally supplying a power supply voltage to the first power supply wire and a second input terminal for externally supplying the power supply voltage to the second power supply wire, and the first and second input terminals may be provided independently of each other.
When the first power supply wire causes a large voltage drop in this case, the second power supply wire is prevented from bad influence thereof exerted through the first and second input terminals.
The semiconductor integrated circuit may further comprise a semiconductor substrate formed with the single or plurality of logic circuits, the first power supply wire and the second power supply wire, and the first and second input terminals may include bonding pads formed on the semiconductor substrate respectively. In this case, voltage drops in the first and second input terminals can be ignored.
The first power supply wire may have a larger width than the second power supply wire. The width of the second power supply wire is preferably small in consideration of area reduction in the overall circuit. On the other hand, a large current instantaneously flows to the first power supply wire. When the width of the first power supply wire is rendered larger than that of the second power supply wire, wiring resistance of the first power supply wire is so reduced that the value of a voltage drop in the first power supply wire can be reduced.
The power supply voltage may include a high-potential side power supply voltage and a low-potential side power supply voltage, the first power supply wire may include a first high-potential side power supply wire for supplying the high-potential side power supply voltage to the first circuit and the second power supply wire may include a second high-potential side power supply wire for supplying the high-potential side power supply voltage to the second circuit, while the semiconductor integrated circuit may further comprise a common low-potential side power supply wire for supplying the low-potential side power supply voltage to the first circuit and the second circuit.
In this case, the first high-potential side power supply wire is connected with the first circuit, while the second high-potential side power supply wire provided independently of the first high-potential side power supply wire is connected with the second circuit. Also when the first high-potential side power supply wire causes a large voltage drop, therefore, no bad influence is exerted to the second high-potential side power supply wire. Therefore, the second circuit can be prevented from a malfunction.
The semiconductor integrated circuit may further comprise a first high-potential side input terminal for externally supplying the high-potential side power supply voltage to the first high-potential side power supply wire, a second high-potential side input terminal for externally supplying the high-potential side power supply voltage to the second high-potential side power supply wire and a low-potential side input terminal for externally supplying the low-potential side power supply voltage to the common low-potential side power supply wire.
The first high-potential side input terminal and the second high-potential side input terminal may be provided in common. Alternatively, the first high-potential side input terminal and the second high-potential side input terminal may be provided independently of each other.
The first high-potential side power supply wire may have a larger width than the second high-potential side power supply wire. Thus, wiring resistance of the first high-potential side power supply wire instantaneously fed with a large current is so reduced that the value of a voltage drop in the first high-potential side power supply wire can be reduced.
The semiconductor integrated circuit may further comprise a semiconductor substrate and a multilayer structure, provided on the semiconductor substrate, forming the single or plurality of logic circuits, the first power supply wire and the second power supply wire, while the multilayer structure may include first and second layers, the low-potential side power supply wire may be formed on the first layer of the multilayer structure, and the first and second high-potential side power supply wires may be formed on the second layer of the multilayer structure.
The power supply voltage may include a high-potential side power supply voltage and a low-potential side power supply voltage, the first power supply wire may include a first high-potential side power supply wire for supplying the high-potential side power supply voltage to the first circuit and a first low-potential side power supply wire for supplying the low-potential side power supply voltage to the first circuit, and the second power supply wire may include a second high-potential side power supply wire for supplying the high-potential side power supply voltage to the second circuit and a second low-potential side power supply wire for supplying the low-potential side power supply voltage to the second circuit.
In this case, the first high-potential side power supply wire and the first low-potential side power supply wire are connected with the first circuit, while the second high-potential side power supply wire provided independently of the first high-potential side power supply wire and the second low-potential side power supply wire provided independently of the first low-potential side power supply wire are connected with the second wire. Also when the first high-potential side power supply wire or the first low-potential side power supply wire causes a large voltage drop, therefore, no influence thereof is exerted on the second high-potential side power supply wire or the second low-potential side power supply wire. Therefore, the second circuit can be prevented from a malfunction.
The semiconductor integrated circuit may include a first high-potential side input terminal for externally supplying the high-potential side power supply voltage to the first high-potential side power supply wire, a second high-potential side input terminal for externally supplying the high-potential side power supply voltage to the second high-potential side power supply wire, a first low-potential side input terminal for externally supplying the low-potential side power supply voltage to the first low-potential side power supply wire and a second low-potential side input terminal for externally supplying the low-potential side power supply voltage to the second low-potential side power supply wire.
The first high-potential side input terminal and the second high-potential side input terminal may be provided in common. Alternatively, the first high-potential side input terminal and the second high-potential side input terminal may be provided independently of each other. Further, the first low-potential side input terminal and the second low-potential side input terminal may be provided in common. Alternatively, the first low-potential side input terminal and the second low-potential side input terminal may provided independently of each other.
The first high-potential side power supply wire may have a larger width than the second high-potential side power supply wire. Thus, wiring resistance of the first high-potential side power supply wire instantaneously fed with a large current is so reduced that the value of a voltage drop in the first high-potential power supply wire can be reduced.
The first low-potential side power supply wire may have a larger width than the second low-potential side power supply wire. Thus, wiring resistance of the first low-potential side power supply wire instantaneously fed with a large current is so reduced that the value of a voltage drop in the first low-potential power supply wire can be reduced.
The semiconductor integrated circuit may further comprises a semiconductor substrate and a multilayer structure, provided on the semiconductor substrate, forming the single or plurality of logic circuits, the first power supply wire and the second power supply wire, and the first and second high-potential side power supply wires and the first and second low-potential side power supply wires may be formed on the same layer of the multilayer structure.
The second circuit may include a holding circuit holding the state of an input signal in response to the clock signal input by the first circuit.
The logic circuit may be formed by a basic cell of a standard cell system or a gate array system.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.